Architectures for Computer Vision From Algorithm to Chip with Verilog

Architectures for Computer Vision From Algorithm to Chip with Verilog

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Architectures for Computer Vision: From Algorithm to Chip with Verilog by Hong Jeong
2014 | ISBN: 111865918X | English | 469 pages | PDF | 7 MB

About the Author
Hong Jeong joined the Department of Electrical Engineering at POSTECH in January 1988, after graduating from the Department of EECS at MIT. He has worked at Bell Labs, Murray Hill, New Jersey and has visited the Department of Electrical Engineering at USC. He has taught integrated courses, such as multimedia algorithms, Verilog HDL design, and recognition engineering, in the Department of Electrical Engineering at POSTECH. He is interested in illing in the gaps between computer vision algorithms and VLSI architectures, using GPU and advanced HDL languages




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