Embedded System Design with Zynq Devices for Newbie

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Embedded System Design with Zynq Devices for Newbie [TutsNode.com] - Embedded System Design with Zynq Devices for Newbie 8. Getting started with Interrupts
  • 3. Using GPIO Interrupt P2.mp4 (218.4 MB)
  • 3. Using GPIO Interrupt P2.srt (31.5 KB)
  • 6. Handling Multiple Interrupts.srt (28.0 KB)
  • 2. Using GPIO Interrupt P1.srt (6.6 KB)
  • 7. SDK Code.html (3.0 KB)
  • 1. Interrupts.html (2.4 KB)
  • 5. SDK Code Slide Switch and LED.html (2.1 KB)
  • 4. SDK Code Button and LED.html (1.9 KB)
  • 6. Handling Multiple Interrupts.mp4 (195.5 MB)
  • 2. Using GPIO Interrupt P1.mp4 (38.1 MB)
2. Getting Started with Simple Peripherals GPIO
  • 4. Working with GPIO LED's.srt (33.2 KB)
  • 1. Zynq Intro.html (1.4 KB)
  • 2. Zynq Peripherals.html (1.4 KB)
  • 3. Zynq Toolchain Configuration Lab.html (0.9 KB)
  • 6. Understanding handling multiple instances of IP's.srt (16.4 KB)
  • 8. Code.html (0.8 KB)
  • 7. Using Multichannel GPIO Instance.srt (13.0 KB)
  • 5. Working with GPIO LED's Understanding Debug.srt (6.9 KB)
  • 4. Working with GPIO LED's.mp4 (210.1 MB)
  • 6. Understanding handling multiple instances of IP's.mp4 (132.6 MB)
  • 7. Using Multichannel GPIO Instance.mp4 (74.9 MB)
  • 5. Working with GPIO LED's Understanding Debug.mp4 (41.7 MB)
1. Toolchain Configuration
  • 2. Code and BD.html (0.8 KB)
  • 5. TCL Script.html (1.0 KB)
  • 1. Introduction.srt (14.0 KB)
  • 4. How to use TCL Script for BD automation.srt (10.4 KB)
  • 3. Understanding useful Files added to Project Directory.srt (5.6 KB)
  • 1. Introduction.mp4 (73.2 MB)
  • 4. How to use TCL Script for BD automation.mp4 (57.9 MB)
  • 3. Understanding useful Files added to Project Directory.mp4 (21.3 MB)
5. Software and Hardware Debugging
  • 6. Getting Started with Integrated Logic Analyzer (ILA).srt (25.6 KB)
  • 5. Using XSCT Console.srt (11.5 KB)
  • 3. Using Breakpoint for Debugging Analyzing Functions.srt (10.1 KB)
  • 2. Using Breakpoint for Debugging Analyzing Variables.srt (10.1 KB)
  • 7. Understanding differences compared to Pure RTL flow.srt (7.8 KB)
  • 1. Using Serial Window for Debugging.srt (6.7 KB)
  • 4. Using Memory Content Viewer.srt (6.3 KB)
  • 6. Getting Started with Integrated Logic Analyzer (ILA).mp4 (157.6 MB)
  • 5. Using XSCT Console.mp4 (71.0 MB)
  • 7. Understanding differences compared to Pure RTL flow.mp4 (43.1 MB)
  • 2. Using Breakpoint for Debugging Analyzing Variables.mp4 (41.1 MB)
  • 3. Using Breakpoint for Debugging Analyzing Functions.mp4 (35.3 MB)
  • 1. Using Serial Window for Debugging.mp4 (33.4 MB)
  • 4. Using Memory Content Viewer.mp4 (32.6 MB)
4. Getting started with Intermediate Drivers Understanding Timers
  • 1. Using Watchdog Timer in Watchdog mode.srt (24.2 KB)
  • 3. SCU Timer in Polled Mode.srt (20.4 KB)
  • 2. SDK Code.html (0.9 KB)
  • 4. Code.html (1.4 KB)
  • 6. Code.html (1.1 KB)
  • 7. SCU Timer Understanding Auto reload mode.srt (7.6 KB)
  • 5. SC Timer Understanding usage of Prescaler.srt (6.5 KB)
  • 1. Using Watchdog Timer in Watchdog mode.mp4 (145.7 MB)
  • 3. SCU Timer in Polled Mode.mp4 (130.8 MB)
  • 7. SCU Timer Understanding Auto reload mode.mp4 (57.9 MB)
  • 5. SC Timer Understanding usage of Prescaler.mp4 (51.3 MB)
9. Fundamentals of Timers AXI Timer, SCU Timer and Watchdog
  • 7. Using SCU Timer in Interrupt Mode.srt (21.5 KB)
  • 11. Using Triple Timer Counter in Interval mode with Interrupts.srt (19.8 KB)
  • 2. Using AXI Timer IP P2 Understanding Down Mode.srt (18.5 KB)
  • 9. Reusing SCU Timer Interrupt Code for Watchdog Timer.srt (14.6 KB)
  • 5. Understanding usage of Timer for Profiling.srt (11.6 KB)
  • 1. Using AXI Timer IP P1 Creating Block Design.srt (3.8 KB)
  • 3. Using AXI Timer IP P2 Understanding Auto-reload Mode.srt (3.5 KB)
  • 12. Code.html (1.7 KB)
  • 10. Code.html (1.4 KB)
  • 8. Code.html (1.3 KB)
  • 6. SDK Code.html (0.9 KB)
  • 4. SDK Code.html (0.8 KB)
  • 11. Using Triple Timer Counter in Interval mode with Interrupts.mp4 (143.8 MB)
  • 9. Reusing SCU Timer Interrupt Code for Watchdog Timer.mp4 (117.2 MB)
  • 7. Using SCU Timer in Interrupt Mode.mp4 (116.9 MB)
  • 2. Using AXI Timer IP P2 Understanding Down Mode.mp4 (98.7 MB)
  • 5. Understanding usage of Timer for Profiling.mp4 (54.9 MB)
  • 3. Using AXI Timer IP P2 Understanding Auto-reload Mode.mp4 (20.8 MB)
  • 1. Using AXI Timer IP P1 Creating Block Design.mp4 (16.2 MB)
3. Getting started with Intermediate Drivers UARTPS
  • 2. Writing Data with UARTPS Drivers.srt (19.0 KB)
  • 1. Zynq Peripherals.html (1.2 KB)
  • 3. Code.html (1.6 KB)
  • 5. Code.html (1.7 KB)
  • 7. Code.html (2.6 KB)
  • 6. Varying Operating Modes with UART PS.srt (8.6 KB)
  • 4. Varying Baud rates with UARTPS Drivers.srt (3.0 KB)
  • 2. Writing Data with UARTPS Drivers.mp4 (108.6 MB)
  • 6. Varying Operating Modes with UART PS.mp4 (45.1 MB)
  • 4. Varying Baud rates with UARTPS Drivers.mp4 (16.4 MB)
7. Understanding Memory Resources
  • 2. Using AXI BRAM with pointers P2.srt (18.5 KB)
  • 5. Handling DDR Transactions.srt (13.5 KB)
  • 7. Handling DDR to BRAM Transactions.srt (11.6 KB)
  • 3. Understanding XIL_IO Drivers.srt (10.8 KB)
  • 4. BRAM RTL Simulation.srt (10.4 KB)
  • 1. Using AXI BRAM with pointers P1.srt (9.6 KB)
  • 6. Code.html (1.0 KB)
  • 2. Using AXI BRAM with pointers P2.mp4 (109.6 MB)
  • 5. Handling DDR Transactions.mp4 (85.2 MB)
  • 7. Handling DDR to BRAM Transactions.mp4 (76.1 MB)
  • 3. Understanding XIL_IO Drivers.mp4 (72.0 MB)
  • 1. Using AXI BRAM with pointers P1.mp4 (59.9 MB)
  • 4. BRAM RTL Simulation.mp4 (59.6 MB)
6. Profiling
  • 1. Understanding Profiling feature of SDK.srt (14.4 KB)
  • 2. Profil

Description


Description

Xilinx Zynq SoC’s are capable of providing maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain. The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller, AXI Timers, GIC etc.
Who this course is for:

Anyone wish to build expertise in Xilinx Zynq APSOC and Vivado SDK Environment
Embedded System Design with FPGA Processors

Requirements

Understanding of Digital Electronics
Fundamentals of Computer Architecture

Last Updated 4/2021



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Embedded System Design with Zynq Devices for Newbie


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Embedded System Design with Zynq Devices for Newbie


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