FPGA Design with MATLAB & Simulink

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[ FreeCourseWeb.com ] Udemy - FPGA Design with MATLAB & Simulink
  • Get Bonus Downloads Here.url (0.2 KB)
  • ~Get Your Files Here ! 1. Section_1 Installation of MatlabSimulink and VIVADOISE
    • 1. Installation of MatlabSimulink and VIVADOISE-en_US.srt (11.4 KB)
    • 1. Installation of MatlabSimulink and VIVADOISE.mp4 (70.8 MB)
    • 2. Section 1 Lab 1 Basic Design with Simulink Environment-en_US.srt (4.8 KB)
    • 2. Section 1 Lab 1 Basic Design with Simulink Environment.mp4 (48.8 MB)
    • Section-1-V2-Installing-Tools-Matlab-Simulink-and-ISE-VIVADO.pdf (1.1 MB)
    2. Section_2 Introduction to HDL Coder and System Generator
    • 1. Introduction to HDL Coder and System Generator Part I-en_US.srt (7.5 KB)
    • 1. Introduction to HDL Coder and System Generator Part I.mp4 (53.3 MB)
    • 2. Introduction to HDL Coder and System Generator Part II-en_US.srt (21.0 KB)
    • 2. Introduction to HDL Coder and System Generator Part II.mp4 (37.3 MB)
    • Section-2-V2-Introduction-to-HDL-Coder-and-System-Generator.pdf (1.9 MB)
    3. Section_3 Project with System Generator
    • 1. Section_3 Basic Project with System Generator Overview-en_US.srt (11.0 KB)
    • 1. Section_3 Basic Project with System Generator Overview.mp4 (55.6 MB)
    • 2. Section 3 Lab 30 Basic Project with System Generator-en_US.srt (12.7 KB)
    • 2. Section 3 Lab 30 Basic Project with System Generator.mp4 (117.2 MB)
    • 3. Lab 31 Basic FFT Design with System Generator-en_US.srt (18.8 KB)
    • 3. Lab 31 Basic FFT Design with System Generator.mp4 (31.6 MB)
    • 4. Lab 32 Creating Custom JTAG Configuration-en_US.srt (6.8 KB)
    • 4. Lab 32 Creating Custom JTAG Configuration.mp4 (17.8 MB)
    • 5. (Optional) Section_3 Lab 32 Demo JTAG Implementation on Spartan 3E from Sys Gen-en_US.srt (0.7 KB)
    • 5. (Optional) Section_3 Lab 32 Demo JTAG Implementation on Spartan 3E from Sys Gen.mp4 (10.6 MB)
    • Section-3-Basic-Project-with-System-Genrator-V2.pdf (1.2 MB)
    4. Section_4 Advance Design with HDL Coder
    • 1. Section 4 Advance Design with HDL Coder Overview-en_US.srt (21.9 KB)
    • 1. Section 4 Advance Design with HDL Coder Overview.mp4 (154.9 MB)
    • 2. LMS Filter Design_Advance Design with HDL Coder-en_US.srt (11.3 KB)
    • 2. LMS Filter Design_Advance Design with HDL Coder.mp4 (28.0 MB)
    • Section-4-Advance-Design-with-HDL-Coder-with-installation-V2.pdf (3.1 MB)
    • hdl_coder_lms
      • lms.slx (17.9 KB)
      • original_speech.wav (3.8 MB)
      • playback.m (0.3 KB)
      • setup.m (0.2 KB)
      5. Section_5 Advanced Design with System Generator
      • 1. Lab 51 FIR Filter Design-en_US.srt (11.8 KB)
      • 1. Lab 51 FIR Filter Design.mp4 (32.7 MB)
      • 2. OFDM Transceiver Design and Simulation Part I Transmitter Section-en_US.srt (13.7 KB)
      • 2. OFDM Transceiver Design and Simulation Part I Transmitter Section.mp4 (18.6 MB)
      • 3. OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation-en_US.srt (8.6 KB)
      • 3. OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation.mp4 (17.7 MB)
      • OFDM_Transceiver.slx (34.5 KB)
      • QAM16_DEM.m (0.7 KB)
      6. Section_6 Zynq Development with System Generator & VIVADO
      • 1. ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator-en_US.srt (8.2 KB)
      • 1. ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator.mp4 (62.7 MB)
      7. Bonus Lecture
      • Bonus Lecture.html (1.0 KB)
      • Bonus Resources.txt (0.3 KB)

Description

FPGA Design with MATLAB & Simulink

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 768 MB | Duration: 2h 52m
What you'll learn
FPGA Development with Matlab and Simulink Tool.
Creating Projects with System Generator and HDL coder
Implementing FIR and IIR Filter on FPGA from System Generator
Implementation of OFDM modulation on FPGA
Zynq FPGA Design with Matlab/Simulink (System Generator)
LMS filter design with HDL coder from Matlab
Requirements
Basic Idea of Matlab and Simulink
FPGA Design Basics
Idea of FPGA Design with Xilinx ISE and VIVADO
Idea of Hardware Description Language
Description
This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".

This course is on Designing FPGA based Signal Processing Projects with MATLAB/Simulink and FPGA Design Tool (Xilinx VIVADO/ISE), we are going to use Xilinx System Generator (interface between MATLAB/Simulink and VIVADO/ISE) and HDL Coder. From this two tools we can design our projects on traditional MATLAB/Sumilink design flow; using Blocks and integrating blocks in Simulink or using MATLAB codes and finally converting this two types of design in to HDL or into Bitstream so we can program FPGA from MATLAB/Simulink or VIVADO/ISE.

We have session on FIR,IIR, LMS Filter Design and OFDM Modulation algorithm implementation on FPGA.

MATLAB & Simulink are the best tools for Signal Processing Projects, while FPGA are best hardware platform for such type of Signal Processing Projects cause of it's flexibility and processing capabilities.

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FPGA Design with MATLAB & Simulink


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FPGA Design with MATLAB & Simulink


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