Udemy - VLSI - Essential concepts and detailed interview guide

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[ DevCourseWeb.com ] Udemy - VLSI - Essential concepts and detailed interview guide
  • Get Bonus Downloads Here.url (0.2 KB)
  • ~Get Your Files Here ! 01 - Physical Design Flow Overview
    • 001 Floor-Planning Steps.mp4 (45.5 MB)
    • 001 Floor-Planning Steps_en.vtt (15.1 KB)
    • 002 Netlist Binding And Placement Optimization.mp4 (65.5 MB)
    • 002 Netlist Binding And Placement Optimization_en.vtt (13.1 KB)
    • 003 Clock Net Shielding.mp4 (62.8 MB)
    • 003 Clock Net Shielding_en.vtt (13.6 KB)
    • 004 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 (106.1 MB)
    • 004 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt (12.7 KB)
    02 - Floorplanning
    • 001 Utilization Factor And Aspect Ratio.mp4 (28.5 MB)
    • 001 Utilization Factor And Aspect Ratio_en.vtt (12.5 KB)
    • 002 Concept of Pre-placed Cells.mp4 (28.8 MB)
    • 002 Concept of Pre-placed Cells_en.vtt (13.3 KB)
    • 003 Power Planning.mp4 (45.6 MB)
    • 003 Power Planning_en.vtt (15.0 KB)
    • 004 Pin Placement And Logical Cell Placement Blockage.mp4 (46.2 MB)
    • 004 Pin Placement And Logical Cell Placement Blockage_en.vtt (13.6 KB)
    03 - Placement
    • 001 Netlist Binding And Placement.mp4 (46.4 MB)
    • 001 Netlist Binding And Placement_en.vtt (13.2 KB)
    • 002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 (91.4 MB)
    • 002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt (14.4 KB)
    • 003 Optimize Placement Continued.mp4 (87.0 MB)
    • 003 Optimize Placement Continued_en.vtt (12.1 KB)
    04 - Timing Analysis With Ideal Clocks
    • 001 Setup Time Analysis And Introduction To Flip-Flop Setup Time.mp4 (31.5 MB)
    • 001 Setup Time Analysis And Introduction To Flip-Flop Setup Time_en.vtt (13.2 KB)
    • 002 Setup Timing Analysis With Multiple Clocks.mp4 (34.3 MB)
    • 002 Setup Timing Analysis With Multiple Clocks_en.vtt (11.7 KB)
    • 003 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 (72.8 MB)
    • 003 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt (12.5 KB)
    • 004 Data Slew Check.mp4 (82.9 MB)
    • 004 Data Slew Check_en.vtt (13.0 KB)
    05 - Clock Tree Synthesis - Introduction And Quality Check Parameters
    • 001 Introduction To Clock Tree Synthesis.mp4 (21.6 MB)
    • 001 Introduction To Clock Tree Synthesis_en.vtt (13.9 KB)
    • 002 Duty Cycle And Latency Check.mp4 (25.0 MB)
    • 002 Duty Cycle And Latency Check_en.vtt (13.4 KB)
    • 003 Latency And Power Check.mp4 (30.7 MB)
    • 003 Latency And Power Check_en.vtt (13.4 KB)
    • 004 Power And Crosstalk Quality Check.mp4 (32.0 MB)
    • 004 Power And Crosstalk Quality Check_en.vtt (14.1 KB)
    • 005 Glitch Quality Check.mp4 (16.9 MB)
    • 005 Glitch Quality Check_en.vtt (10.1 KB)
    06 - H-Tree
    • 001 H-Tree Algorithm And Skew Check.mp4 (22.3 MB)
    • 001 H-Tree Algorithm And Skew Check_en.vtt (13.6 KB)
    • 002 H-Tree Pulse Width And Duty Cycle Check.mp4 (48.5 MB)
    • 002 H-Tree Pulse Width And Duty Cycle Check_en.vtt (13.3 KB)
    • 003 H-Tree Latency And Power Check.mp4 (55.6 MB)
    • 003 H-Tree Latency And Power Check_en.vtt (13.3 KB)
    07 - Clock Tree Modelling and Observations
    • 001 Clock Tree Modelling.mp4 (24.9 MB)
    • 001 Clock Tree Modelling_en.vtt (12.8 KB)
    • 002 Clock Tree Building.mp4 (39.4 MB)
    • 002 Clock Tree Building_en.vtt (13.3 KB)
    • 003 Clock Tree Observations.mp4 (48.3 MB)
    • 003 Clock Tree Observations_en.vtt (13.0 KB)
    08 - Buffered H-Tree
    • 001 H-Tree Buffering Observations.mp4 (60.5 MB)
    • 001 H-Tree Buffering Observations_en.vtt (15.2 KB)
    • 002 H-Tree Pulse Width Check And Issues With Regular Buffers.mp4 (45.5 MB)
    • 002 H-Tree Pulse Width Check And Issues With Regular Buffers_en.vtt (12.6 KB)
    • 003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution.mp4 (63.7 MB)
    • 003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution_en.vtt (13.2 KB)
    • 004 H-Tree Clock Buffers And Pulse Width Check.mp4 (65.5 MB)
    • 004 H-Tree Clock Buffers And Pulse Width Check_en.vtt (14.5 KB)
    • 005 Dynamic Power And Short Circuit Power.mp4 (58.3 MB)
    • 005 Dynamic Power And Short Circuit Power_en.vtt (13.0 KB)
    09 - Clock Tree Optimization Checklist
    • 001 Optimization Checklist.mp4 (26.2 MB)
    • 001 Optimization Checklist_en.vtt (13.4 KB)
    • 002 Leakage Current Reduction Technique.mp4 (26.3 MB)
    • 002 Leakage Current Reduction Technique_en.vtt (13.1 KB)
    • 003 Optimized Clock Tree Power And Latency Check.mp4 (30.9 MB)
    • 003 Optimized Clock Tree Power And Latency Check_en.vtt (9.0 KB)
    10 - Static Timing Analysis With Real Clocks
    • 001 Static Timing Analysis With Real Clocks.mp4 (32.0 MB)
    • 001 Static Timing Analysis With Real Clocks_en.vtt (13.6 KB)
    • 002 Impact Of Unbalanced Skew On Setup Time.mp4 (52.8 MB)
    • 002 Impact Of Unbalanced Skew On Setup Time_en.vtt (13.4 KB)
    • 003 Impact Of Unbalanced Skew On Hold Time.mp4 (55.7 MB)
    • 003 Impact Of Unbalanced Skew On Hold Time_en.vtt (15.7 KB)
    11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP
    • 001 Introduction.mp4 (18.6 MB)
    • 001 Introduction_en.vtt (11.1 KB)
    • 002 Dominant Lateral Capacitance.mp4 (57.3 MB)
    • 002 Dominant Lateral Capacitance_en.vtt (13.1 KB)
    • 003 Noise Margin Voltage Parameters.mp4 (32.5 MB)
    • 003 Noise Margin Voltage Parameters_en.vtt (10.7 KB)
    • 004 Lower Supply Voltage.mp4 (29.4 MB)
    • 004 Lower Supply Voltage_en.vtt (13.4 KB)
    12 - Glitch Examples And Factors Affecting Glitch Height
    • 001 Basic Crosstalk Glitch Example.mp4 (29.2 MB)
    • 001 Basic Crosstalk Glitch Example_en.vtt (13.8 KB)
    • 002 Glitch Discharge With High Drive Strength PMOS Transistor.mp4 (34.9 MB)
    • 002 Glitch Discharge With High Drive Strength PMOS Transistor_en.vtt (1

Description

VLSI - Essential concepts and detailed interview guide



https://DevCourseWeb.com

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 2.74 GB | Duration: 11h 20m

VLSI Academy

What you'll learn
To bridge the gap between Understanding and Application of Knowledge, this leads to innovation
Requirements
Individuals having Basic Knowledge of Electrical and Electronics
Description
This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.

This course covers most topics in brief and not in detail, just to revise topics below interviews. For detailed and thorough discussion of each topic, you need to go to individual courses.



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Udemy - VLSI - Essential concepts and detailed interview guide


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Udemy - VLSI - Essential concepts and detailed interview guide


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